The present invention relates to a semiconductor memory device, and more particularly, to a circuit and method for controlling local data lines, which can reduce loading on the local data lines.
There is a need for a circuit for data transmission between a global data line GIO and a local data line LIO. The local data line receives an output from a bit line sense amplifier which is provided from the inside of a memory cell region. The global data line is an input/output data line for data transmission between a data input/output pad and the memory cell region. To this end, an input/output sense amplifier IOSA is used to transmit data loaded on the LIO line to the GIO line during a read operation.
In addition, a memory cell array has a matrix form which consists of a plurality of rows that often calls word lines and a plurality of columns that often calls bit lines. A predetermined address is assigned to each of the rows and columns, wherein a row address is used to designate a particular row and a column address is used to designate a particular column.
FIG. 1 shows the arrangement of a local data line in a conventional memory device. FIG. 2 is a conventional circuit diagram for controlling local data lines.
As shown in FIG. 2, the local data line LIO serves to transfer cell data to a bit line BL selected when a transistor MN4 is turned on by a bit line selection signal BISH. Also, the local data line LIO serves to transfer the data on the bit line BL to a segment input/output line SIO when a transistor MN3 is turned on by a control signal YS in response to a read address.
When a transistor MN1 is turned on by a line switch control signal IOSW, the data on the segment input/output line SIO is then transferred to the local data line LIO. Next, the data on the local data line LIO is amplified by an input/output sense amplifier IOSA and then fed to the global line GIO.
In the arrangement of such conventional local data line, X direction is determined by an active command when a semiconductor memory device is operated, and a row address enable signal ROW ADDRESS EN is activated by the active command and bank information. The activated row address enable signal is utilized to select a corresponding mat array in an X axis direction by logic operation of a row address.
The conventional local data lines with the configuration as above are composed of 128 lines depending on the type of the semiconductor memory device. The local data lines have a capacitance of about 350-770 fF for a semiconductor memory device of 1 Gbyte.
That is, a corresponding word line out of X axis directional mat is activated by an active command and then a line switch control signal IOSW is activated to establish a short-circuit between the segment input/output line SIO and the local data line LIO.
A sense amplifier 10 or 20 amplifies corresponding cell data and waits for a read command. Based on the read command and column address information, a control signal YS is determined. Based on the control signal YS, data of the sense amplifier 10 or 20 out of a sense amplifier array is loaded on the segment input/output line SIO to be transferred. A charge on the segment input/output line SIO is shared with the bit line. Therefore, the data loaded on the segment input/output line SIO is transferred to the local data line LIO connected by the IOSW.
In the meantime, a series of processes as below are performed until the data amplified by the sense amplifier 10 or 20 is transferred to the local data line LIO by the control signal YS.
A bit line BL has a capacitance of about 70 fF. The charge stored in the capacitance is charge shared to be equal to a sum of capacitance of the segment input/output line SIO and capacitance of the local data line LIO.
Meanwhile, the semiconductor memory device is provided with an input/output sense amplifier IOSA. Data transferred to the local data line LIO from the sense amplifier is again amplified and outputted to the global data line GIO. The input/output sense amplifier requires voltage (delta-V) within a certain range. In general, the input/output sense amplifier requires a voltage of 250 mV or more.
Therefore, as the local data line LIO is long in length, a large amount of charge should be derived from the bit line BL and a voltage obtained also becomes small for the same amount of charge. Thus, the decrease in line loading on the local data line will decrease current consumption and improve data processing speed.
In the conventional structure of local data line, however, line loading on the local data line is maintained constantly, regardless of where cell mat is. This structure causes unnecessarily excessive loading on data closer to the input/output sense amplifier, which leads to unnecessary reduction in characteristics.